1. Field of the Invention
The present invention refers to a semiconductor device fabrication method. More particularly, the present invention relates to a fabrication method for metal lines in a semiconductor integrated circuit.
2. Description of the Related Art
A typical semiconductor device includes transistors, resistors and capacitors, and requires metal lines for fabricating a semiconductor device on a silicon wafer. Because the metal lines transmit electric signals, it is necessary for the metal lines to have a low electric resistance. Ideally, metal lines are also inexpensive and highly reliable. Aluminum (Al) is one of several materials that satisfy the above-described requirements. Accordingly, an aluminum layer is widely used as a metal line.
Further, the greater the degree of integration of a semiconductor device, the more narrow each metal line is required to be. Moreover, the thinner a metal line is the smaller the size a contact hole becomes. As the size of the contact hole decreases, an aspect ratio is increased. An increase in the aspect ratio increases the difficulty of filling the contact hole with aluminum. Therefore, the technology capable of completely filling the contact hole with aluminum becomes increasingly important as the degree of integration of a semiconductor device increases.
One technology that has the potential for completely filling a contact hole, having a high aspect ratio, with aluminum is a chemical vapor deposition aluminum (CVD-Al) process. In general, there are two types of CVD-Al processes. The first type is a blanket aluminum process. The second type is a selective aluminum process.
The blanket aluminum process is one technology, which utilizes a characteristic of excellent step coverage in aluminum metals. The blanket Al process deposits aluminum metals on the entire surface of a wafer to fill completely a contact hole. However, as is generally known, the CVD-Al process possesses a peculiar growth characteristic beyond a certain thickness, thereby generating a rougher wafer surface and not filling a small contact hole.
Alternatively, the selective Al process, which utilizes a difference in a growth rate between an insulation layer and a conductive layer, may only be employed in a limited area, such as a via contact. The selective Al process may not be employed as a metal contact depositing a barrier metal.
Therefore, new technology for lowering contact resistance and metal line resistance and for completely filling a contact hole is necessary to present day and future integrated semiconductor devices.
Referring to FIG. 1A, using a conventional preferential metal deposition (PMD) process, an insulation layer 3 is deposited on a silicon substrate 1. After generating a contact hole 35, a barrier metal is deposited on the contact hole 35 and the insulation layer 3. Then, an anti-nucleation layer (ANL) 7 is generated on the surface of the barrier metal 5, except at the location of the contact hole 35.
A physical vapor deposition (PVD) process, or a CVD process, in a condition of poor conformability, deposits an oxidation metal such as aluminum (Al), zirconium (Zr), titanium (Ti), strontium (Sr), magnesium (Mg), barium (Ba), calcium (Ca), cerium (Ce), or yttrium (Y), etc. Subsequently, either the PVD process or the CVD process is utilized to oxidize the deposited metal layer by exposing the layer to air or by use of an oxygen plasma process to generate the ANL layer 7.
Referring to FIG. 1B to FIG. 1D, a CVD-Al process is used to deposit a metal layer 9 selectively in the contact hole 35. Subsequently, a physical vapor deposition aluminum (PVD-Al) process is used to deposit an aluminum layer 11 and the contact hole 35 is filled using a re-flow process.
However, referring to FIG. 3A, the above-mentioned technology has a problem in generating abnormal growth patterns, such as a whisker type CVD-Al 15 when the ANL layer 7 is not entirely deposited on the surface of the barrier metal 5. Use of such a conventional CVD-Al creates problems in the following process, which results in lowered yields.
On the contrary, referring to FIG. 3B, the abnormal growth of the CVD-Al does not occur when the ANL layer 7 is deposited on the entire surface of the barrier metal 5. The results, as illustrated in FIG. 3B, represent a significant improvement over those of the prior art and may be achieved by use of the present invention.
As depicted in FIG. 4, when an ANL layer does not cover completely a barrier metal because of surface roughness or grains of the barrier metal, the CVD-Al is grown abnormally and selectively in the area of the barrier metal. In FIG. 4, the barrier metal is a conductive layer consisting of titanium Ti or titanium nitride TiN.
In an effort to overcome at least some of the above-described problems, a feature of a preferred embodiment of the present invention provides a fabrication method in a semiconductor integrated circuit controlling an abnormal growth of a CVD-Al.
The preferred embodiments of the present invention provide a semiconductor device fabrication method having a recess region in an insulation layer on a silicon substrate, including depositing a barrier metal, on the entire surface of the insulation layer, filling the recess region with an oxide layer, removing the barrier metal on an upper side of the insulation layer, removing the oxide layer in the recess region and exposing the barrier metal of the recess region, depositing a CVD-Al layer on the barrier metal, and depositing a PVD-Al layer on the CVD-Al layer and re-flowing the PVD-Al layer.